Semiconductor components can be manufactured using wafer level fabrication processes in which multiple components are contained on a single substrate. Semiconductor dice, for example, are typically fabricated on substrates in the form of silicon wafers. Following the fabrication process, the dice can be singulated into individual units.
Semiconductor packages, such as BGA packages, can also be manufactured using wafer level fabrication processes. A BGA package includes an array of external ball contacts, such as solder balls, that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component. Some BGA packages have a foot print that is about the size of the die contained in the package. These BGA packages are also known as chip scale packages.
Multiple BGA packages can be fabricated on a single substrate formed of an electrically insulating material. Sometimes the substrate comprises a reinforced polymer laminate, such as bismaleimide triazine (BT), or an epoxy resin (e.g., FR-4). BGA packages can also be fabricated using ceramic or silicon substrates. The substrate can be in the form of a wafer, or in the form of a panel of material.
During, or following, the fabrication process it is usually necessary to perform test procedures on the components to evaluate various electrical characteristics of the components. For example, wafer probe testing can be used to evaluate the gross functionality of dice contained on a wafer.
In order to perform the test procedures it is necessary to make temporary electrical connections with contacts on the components. Semiconductor dice typically include contacts in the form of planar aluminum bond pads, or bond pads bumped with solder bumps. Semiconductor packages typically include contacts in the form of solder balls arranged in a dense area array. For making these temporary electrical connections an interconnect is employed. A wafer probe card is one type of interconnect, and includes probe needles that electrically engage the bond pads on the wafer.
As semiconductor components become smaller, and the contacts on the components become more dense, the temporary electrical connections with the contacts become more difficult to make. Variations in the size and location of the contacts also make the temporary electrical connections difficult to make. In particular, the z-direction location and planarity of contacts can vary between different components on a substrate, and can vary between contacts on the same component. This makes it difficult to make reliable electrical connections with the contacts.
In addition, the contacts can be damaged by the interconnect. Solder balls are particularly susceptible to deformation and loosening of the solder joints that hold the balls on the components. Also, native oxide layers are usually present on the component contacts, and these oxide layers must be penetrated by the contacts on the interconnect. This requires application of forces for scrubbing or penetrating the contacts on the components.
The present invention is directed to an interconnect that can be used to test multiple components contained on a substrate. The interconnect includes contacts that are configured to accommodate dimensional variations, and to accommodate different z-axis locations of the contacts on the components.